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Please note: These parts are pulls! Bridge Between the PCI Bus and ISA Bus PCI and ISA Master/Slave Interface Supports PIO and Bus Master IDE 8 x 32-Bit Buffer for Bus Master IDE PCI Burst Transfers Separate Master/Slave IDE Mode Support (PIIX3) Plug-n-Play Port for Motherboard Devices 2 Steerable DMA Channels (PIIX Only) Fast DMA with 4-Byte Buffer (PIIX Only) 2 Steerable Interrupts Lines on the PIIX and 1 Steerable Interrupt Line on the PIIX3 Steerable PCI Interrupts for PCI Device PlugnPlay PCI Specification Revision 2.1 Compliant (PIIX3) Functionality of One 82C54 Timer System Timer; Refresh Request; Speaker Tone Output Two 82C59 Interrupt Controller Functions Independently Programmable for Edge/Level Sensitivity 7 Independently Programmable Channels Controls Lower X-Bus Data Byte Transceiver I/O Advanced Programmable Interrupt Controller (IOAPIC) Support (PIIX3) Universal Serial Bus (USB) Host Controller (PIIX3) Compatible with Universal Host Controller Interface (UHCI) Contains Root Hub with 2 USB Ports System Power Management (Intel SMM Support) Programmable System Management Interrupt (SMI)—Hardware Events, Software Events, EXTSMI# Programmable CPU Clock Control (STPCLK#) NAND Tree for Board-Level ATE Testing The 82371FB (PIIX) and 82371SB (PIIX3) PCI ISA IDE Xcelerators are multi-function PCI devices implementing a PCI-to-ISA bridge function and an PCI IDE function. In addition, the PIIX3 implements a Universal Serial Bus host/hub function. As a PCI-to-ISA bridge, the PIIX/PIIX3 integrates many common I/O functions found in ISA-based PC systems—a seven-channel DMA controller, two 82C59 interrupt controllers, an 8254 timer/counter, and power management support. In addition to compatible transfers, each DMA channel supports type F transfers. Chip select decoding is provided for BIOS, real time clock, and keyboard controller. Edge/Level interrupts and interrupt steering are supported for PCI plug and play compatibility. The PIIX/PIIX3 supports two IDE connectors for up to four IDE devices providing an interface for IDE hard disks and CD ROMs. The PIIX/PIIX3 provides motherboard plug and play compatibility. PIIX mplements two steerable DMA channels (including type F transfers) and up to two steerable interrupt lines. PIIX3 implements one steerable interrupt line. The interrupt lines can be routed to any of the available ISA interrupts. Both PIIX/PIIX3 implement a programmable chip select. And we salute our friends in other countries around the world! (82371 / SB82371FB / SB82371 / intel integrated circuit is the responsibility of Deana Britt) |
d.britt@cedar--rapids.com (Deana Britt) for more information.
